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Freescale Semiconductor Technical Data
MPC9817 Rev 1, 11/2004
Clock Generator for PowerQUICC and PowerPC Microprocessors and Microcontrollers
The MPC9817 is a PLL-based clock generator specifically designed for Freescale Semiconductor Microprocessor and Microcontroller applications including the PowerPC and PowerQUICC. This device generates the microprocessor input clock and other microprocessor system and bus clocks at any one of four output frequencies. These frequencies include the popular 33- and 66-MHz PCI bus frequencies. The device offers five low-skew clock outputs plus three reference outputs. The clock input reference is 25 MHz and may be derived from an external source or by the addition of a 25-MHz crystal to the on-chip crystal oscillator. The extended temperature range of the MPC9817 supports telecommunication and networking requirements. Features * * * * * * * * * * 5 LVCMOS outputs for processor and other system circuitry 3 Buffered 25-MHz reference clock outputs Crystal oscillator or external reference input 25-MHz input reference frequency Selectable output frequencies include: 25, 33, 50, or 66 MHz Low cycle-to-cycle and period jitter Package: 20-lead SSOP 3.3-V supply Supports computing, networking, and telecommunications applications Ambient temperature range: -40C to +85C
MPC9817
MICROPROCESSOR CLOCK GENERATOR
SD SUFFIX 20 SSOP PACKAGE CASE 1461-01
EN SUFFIX 20 SSOP PACKAGE Pb-FREE PACKAGE CASE 1461-01
Functional Description The MPC9817 uses a PLL with a 25-MHz input reference frequency to generate a single bank of five configurable LVCMOS output clocks. The output frequency of this bank is configurable to either 25, 33, 50, or 66 MHz by two FSEL pins. The 25-MHz reference may be either an external frequency source or a 25-MHz crystal. The 25-MHz crystal is directly connected to the XTAL_IN and XTAL_OUT pins with no additional components required. An external reference may be applied to the XTAL_IN pin with the XTAL_OUT pin left floating. The input reference, whether provided by a crystal or an external input, is also directly buffered to a second bank of three LVCMOS outputs. These outputs may be used as the clock source for processor I/O applications such as an Ethernet PHY. When FSEL0 and FSEL1 are both configured low, the QA outputs are directly fed from the input reference providing a total of eight low-skew 25-MHz outputs. For all other combinations of FSEL0 and FSEL1 the single-ended LVCMOS outputs provide five low-skew outputs for use in driving a microprocessor or microcontroller clock input as well as other system components. The MPC9817 is packaged in a 20-lead SSOP package.
(c) Freescale Semiconductor, Inc., 2004. All rights reserved.
QA0 XTAL_IN OSC XTAL_OUT Ref PLL 400 MHz QA1 33,50,66 MHz QA2 QA3 FSEL0 FSEL1 Data Generator 25 MHz QA4
QREF0
QREF1
QREF2 MR/OE
Figure 1. MPC9817 Logic Diagram
Table 1. Pin Configurations
Pin QA0, QA1, QA2, QA3, QA4 QREF0, QREF1, QREF2 XTAL_IN XTAL_OUT FSEL0, FSEL1 MR/OE VDD GND I/O Output Output Input Output Input Input -- -- Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS -- -- Clock Outputs Reference Output (25 MHz) Crystal Oscillator Input Pin Crystal Oscillator Output Pin Configures Bank A Clock Output Frequency (pull-up) Enables All Outputs (pull-down) 3.3-V Supply Ground Function
Table 2. Function Table
Control FSEL0,FSEL1 Default 11 00 25 MHz fed directly from reference input, PLL disabled 01 33 MHz 10 50 MHz 11 66 MHz
MPC9817 2 Advanced Clock Drivers Devices Freescale Semiconductor
XTAL_IN XTAL_OUT FSEL0 VDD FSEL1 QREF2 GND QREF1 QREF0 VDD
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VDD QA4 QA3 GND QA2 QA1 VDD QA0 MR/OE GND
Figure 2. MPC9817 20-Lead SSOP Package Pinout (Top View)
MPC9817 OPERATION
Crystal Oscillator The MPC9817 features a fully integrated Pierce oscillator to minimize system implementation costs. Other than the addition of a 25-MHz crystal, no external components are required.The crystal selection should be: 25 MHz, parallel resonant type with a load specification of CL = 10 pF. Crystals with a load specification of CL = 20 pF may be used, however, Table 3. Crystal Specifications
Parameter Crystal Cut Resonance Shunt Capacitance (CL) Load Capacitance (CO) Equivalent Series Resistance (ESR) Value Fundamental AT Cut Parallel Resonance 5-7 pF 10 pF 20-60
the reference frequency may be higher than the specified 25 MHz. Externally supplied capacitors on both the XTAL_IN and XTAL_OUT pins may be used to trim the frequency as desired. The crystal should be located as close to the MPC9817 XTAL_IN and XTAL_OUT pins as possible to avoid any board level parasitic.
Power Supply Bypassing The MPC9817 should have all VDD pins bypassed with 0.01 capacitors and a minimum of one 1.0 capacitor for the overall package. All capacitors should be located as close to the SSOP pins as possible.
External Clock Source An external reference source of 25 MHz may be applied to the XTAL_IN pin. In this mode of operation, the XTAL_OUT pin should be left floating.
MPC9817 Advanced Clock Drivers Devices Freescale Semiconductor 3
Table 4. Absolute Maximum Ratings(1)
Symbol VDD IIN IOUT TS Supply Voltage DC Input Current DC Output Current Storage Temperature Characteristics Min -0.3 -- -- -65 Max 3.8 20 75 125 Unit V mA mA C Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
Table 5. General Specifications
Symbol VTT MM HBM LU CIN JA TC Characteristics Output Termination Voltage ESD Protection (machine model) ESD Protection (human body model) Latch-Up Immunity Input Capacitance Thermal Resistance (junction-to-ambient) Ambient Temperature Min -- 200 2000 200 -- -- -40 Typ VDD / 2 -- -- -- 4 80.8 Max -- -- -- -- -- -- 85 Unit V V V mA pF C/W C Inputs Condition
Table 6. DC Characteristics (VDD = 3.3 V 5%, TA = -40 to +85C)
Symbol VIH VIH VIL IIN VOH VOL ZOUT IDD Characteristics Input High Voltage (XTAL_IN) Input High Voltage Input Low Voltage Input Current
(1)
Min 2.4 2.0 -- -- 2.4 -- -- --
Typ -- -- -- -- -- -- 14 8.0
Max VDD + 0.3 VDD + 0.3 0.8 150 -- 0.4 -- 15.0
Unit V V V A V V mA
Condition Input threshold = VDD/2
LVCMOS VIN = VDDL or GND IOH = -12 mA IOL = 12 mA
Output High Voltage Output Low Voltage Output Impedance Maximum Quiescent Supply Current
VDD pins
1. Inputs have pull-down resistors affecting the input current.
MPC9817 4 Advanced Clock Drivers Devices Freescale Semiconductor
Table 7. AC Characteristics(1) (2) (VDD = 3.3 V 5%, TA = -40 to +85C)
Symbol Characteristics Min Typ Max Unit Condition Input and Output Timing Specification fref fVCO fMCX Input Reference Frequency VCO Frequency Range Output Frequency (QAx) FSEL0, FSEL1 = 00 FSEL0, FSEL1 = 01 FSEL0, FSEL1 = 10 FSEL0, FSEL1 = 11 10 47.5 Crystal(3) External Reference PLL Specifications BW tLOCK PLL Closed Loop Bandwidth(4) Maximum PLL Lock Time 500 10 kHz ms 25 MHz Input XTAL Input -- 25 25 400 25 33 50 66 25 -- 50 -- -- -- -- -- -- -- -- -- 52.5 100 0 MHz MHz MHz MHz MHz MHz MHz MHz ns % ppm ppm With recommended crystal see Table 3 PLL locked
Output Frequency (QREFx) frefPW DC fout Reference Input Pulse Width Output Duty Cycle Output Frequency Accuracy
@ 25 MHz
Skew and Jitter Specifications tsk(O) tsk(O) tJIT(CC) tJIT(PER) tr, tf 1. 2. 3. 4. Output-to-Output Skew (within a bank) Output-to-Output Skew (between bank A and bank Ref) Cycle-to-Cycle Jitter Period Jitter Output Rise/Fall Time 100 200 150 100 1 ps ps ns ps FSEL0, FSEL1 = 00 @ 25 MHz Input Reference QA output @ 25 MHz Input Reference QA output 20% to 80%
AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 to VTT. Based upon recommended crystal specifications as outlined in operation section. -3 dB point of PLL transfer characteristics.
Pulse Generator Z = 50
Z = 50
Z = 50
RT = 50 VTT
DUT MPC9817
RT = 50 VTT
Figure 3. MPC9817 AC Test Reference (LVCMOS Outputs)
MPC9817 Advanced Clock Drivers Devices Freescale Semiconductor 5
Table 8. MPC9817 Pin List
Pin 1 2 3 4 5 6 7 8 9 10 Description XTAL_IN XTAL_OUT FSEL0 VDD FSEL1 QREF2 GND QREF1 QREF0 VDD Pin 11 12 13 14 15 16 17 18 19 20 Description GND MR/OE QA0 VDD QA1 QA2 GND QA3 QA4 VDD
MPC9817 6 Advanced Clock Drivers Devices Freescale Semiconductor
PACKAGE DIMENSIONS
.236 .157 .150 PIN 1 ID 5 D 4 .061 .055
18X 1 20
.025
B 4 B
B 4 A .0125 .344 .337 5 C L
10
11
.118
2X 10 TIPS
2X
3 .003 H A-B D
H
C
20X
SEATING PLANE
.010 C
A-B D
.004 C
7
A
NOTES: 1. DIMENSIONS ARE IN INCHES. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUM PLANE H LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE. 4. DATUM A, B AND D TO BE DETRMINED WHERE CENTERLINE BETWEEN LEADS EXITS PLASTIC BODY AT DATUM PLANE H. 5. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS, BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006 INCHES FOR ENDS AND .008 INCHES FOR SIDES. 6. THIS DIMENSION IS LENGTH OF TERMINAL FOR SOLDERING A SUBSTRATE. 7. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN .004 INCHES AT SEATING PLANE. 8. THIS DIMENSION IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY.
A 0 (.010) .010 .007 .012 .008 .007
M MIN BASE METAL
R.003 MIN (.008) .010
GAUGE PLANE PLATING
.0098 .0040
8
C A-B D
8 0
.035 .016
6
SECTION A-A
SECTION B-B
CASE 1461-02 ISSUE O 20 SSOP PACKAGE
MPC9817 Advanced Clock Drivers Devices Freescale Semiconductor 7
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MPC9817 Rev. 1 11/2004

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